It is well known that ionizing radiation (such as gamma rays, x-rays, electrons, and protons) cause degradation of electronic integrated circuits, especially semiconductor integrated circuits. Several different radiation effects have been observed since the 1970's, and have been studied for several decades following the first observations. One effect of ionizing radiation on metal oxide semiconductor (MOS) integrated circuits is a cumulative degradation of the circuit due to trapping of radiation induced charges in the dielectric layers and gate regions and at the silicon silicon-dioxide interface of MOS devices. The deleterious effects include an increase in leakage currents and threshold voltage shifts due to the trapped holes (and/or interface traps, border traps, or other similar trapped charge states). A review of such total ionizing dose (TID) effects has been provided by Barnaby (H. J. Barnaby, “Total-Ionizing-Dose Effects in Modern CMOS Technologies”, IEEE Transactions on Nuclear Science Volume 56 Number 6, pp 3103-3121, 2006).
Another class of ionizing radiation damage is called single event effects (SEE's). Single event effects result from a transient deposition of charge in the integrated circuit due to a single heavy ion, a single proton, or other single particle. An SEE may cause an upset in the value of a memory bit, a transient analog signal, an electrical latch-up, a gate dielectric rupture, or many other events. Some such SEE's cause irreversible damage to the integrated circuit, such as in single event latch-up (SEL). Other SEE events only cause loss of data, and may be recovered by re-writing the effected memory location with the correct data, as in single event upset (SEU).
Process independent approaches utilizing device and circuit design techniques have also been utilized, but these methods resulted in inferior electrical performance and increased circuit size. All of these hardening approaches are well known in the art and have proved very effective in mitigating and/or preventing total ionizing dose changes in MOS integrated circuits specifically designed or re-designed for use in radiation environments. What is desired, therefore, is an integrated circuit wafer structure and corresponding method that is radiation hardened, yet maintains good electrical performance without the penalty of increased circuit size.